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rev. 1.3 10/06 copyright ? 2006 by silicon laboratories aero+ aero+ a ero ? + t ransceiver for gsm and gprs w ireless c ommunications features applications description the aero ? + transceiver is a complete rf front end for multi-band gsm and gprs wireless communications. no external if saw filter or vco modules are required as all functions are completely implemented on- chip, resulting in a dramatic reduction of board area and component count. the aero+ transceiver includes a digitally-controlled crystal oscillator (dcxo) that completely in tegrates the reference oscillator and varactor. functional block diagram low-if receiver: dual or triple-band lna image-reject down-converter universal baseband interface: digital if to baseband converter channel filter and gain control analog or digital i/q interface offset-pll transmitter: integrated tx vco and loop filter dual rf synthesizer: integrated rf and if vcos, loop filters, varactors, and resonators integrated refe rence oscillator: 13 or 26 mhz operation quad-band support: gsm 850 class 4, small ms e-gsm 900 class 4, small ms dcs 1800 class 1 pcs 1900 class 1 gprs class 12 compliant cmos process technology low profile packages: si4200: 5 x 5 mm qfn32 si4201: 4 x 4 mm qfn20 si4134t: 5 x 5 mm qfn32 3-wire serial interface 2.7 v to 3.0 v operation multi-band gsm/gprs di gital cellular handsets multi-band gprs data modems and terminals adc adc pga pga lna lna lna si4200 if pll rf pll si4134t gsm dcs pcs gsm dcs pcs dcxo 0 / 90 antenna switch det baseband dac dac pga pga channel filter 100 khz si4201 i q i q pa pa afc xout patents pending pin assignments (top view) si4200-g-gm (si4200db-bm see page 39) si4201-bm si4134t-bm ordering information: see page 42. gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 v dd pdn gnd nc nc gnd vdd rfog rfidp rfidn rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8 gnd pad 1 2 3 16 17 18 19 20 gnd rxqp rxqn rxip rxin vdd xin gnd ckp ckn v dd xout sdi sclk sen iop ion xen pdn sdo 11 12 13 14 15 6 7 8 9 10 4 5 gnd pad 1 2 3 25 26 27 28 29 30 31 32 iflb ifla gnd vdd pdn xdrven gnd xdrv nc nc xtal1 xtal2 xtalen xafc sen sclk gnd v dd iflop iflon vdd rflop rflon gnd gnd rfld sdi sdo rflc gnd nc gnd 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8
aero+ 2 rev. 1.3
aero+ rev. 1.3 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical triple-band applic ation schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1. receive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2. transmit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4. vco inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5. dcxo overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.6. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.7. xdrv buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8. xout buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 6. pin descriptions: si4200-g- gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7. pin descriptions: si4200db-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8. pin descriptions: si4201-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9. pin descriptions: si4134t-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 10. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11. package outline: si4200-g- gm and si4200db-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 12. package outline: si4201-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13. package outline: si4134t-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
aero+ 4 rev. 1.3 1. electrical specifications table 1. recommended operating conditions 1,2 parameter symbol test condition min typ max unit ambient temperature t a ?202585c supply voltage v dd 2.7 2.85 3.0 v supply voltages difference v ?0.3 ? 0.3 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at 2.85 v and an o perating temperature of 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. 2. supply voltage difference specificatio n applies to power supply pins per ic. table 2. absolute maximum ratings 1,2 parameter symbol value unit dc supply voltage v dd ?0.5 to 3.3 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v dd + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 10 dbm notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the si4200 and si4134t devices are high-performance rf integrated circuits with an esd rating of < 2 kv. handling and assembly of these devices should only be done at esd-protected workstations. 3. for signals sclk, sdi, sen , pdn , xin, xen, xtalen, and xdrven. 4. at saw filter output for all bands.
aero+ rev. 1.3 5 table 3. dc characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit si4200 supply current i rx0 receive mode ? 55 80 ma i tx0 transmit mode ? 60 80 ma i pdn0 pdn =0 ? 1 50 a si4201 supply current 1 i rx1 receive mode ? 9 12 ma i pdn1 pdn =0, xen=0, xbuf = 0, xpd1 = 1 ?150a i xout1 pdn = 0, xen = 1 ? 1 2 ma si4134t supply current 2 i rx3 receive mode ? 18 22 ma i tx3 transmit mode ? 24 30 ma i pdn3 pdn = 0, xtalen = 0 ? 1 50 a i xtal13 pdn = 0, xtalen = 1, f ref =13mhz ?2.53.5ma i xtal26 pdn = 0, xtalen = 1, f ref =26mhz ?3.04.0ma total chipset supply current i rx receive mode ? 83 ? ma i tx transmit mode ? 85 ? ma high level input voltage 3 v ih 0.7 v dd ?? v low level input voltage 3 v il ? ? 0.3 v dd v high level input current 3 i ih v ih =v dd =3.0v ?10 ? 10 a low level input current 3 i il v il =0v, v dd =3.0v ?10 ? 10 a high level output voltage 4 v oh i oh =?500a v dd ?0.4 ? ? v low level output voltage 4 v ol i ol =500a ? ? 0.4 v high level output voltage 5 v oh i oh =?10ma v dd ?0.4 ? ? v low level output voltage 5 v ol i ol =10ma ? ? 0.4 v notes: 1. measured with load on xout pin of 10 pf and f ref = 13 mhz. limits with xen = 1 guaranteed by characterization. 2. rf1 vco is used for receive mode, rf2 and if vcos are used for transmit mode. center frequencies for each vco are as follows: rf1 = 1.9 ghz, rf2 = 1.35 ghz, if = 825 mhz, f ref =13mhz. 3. for pins sclk, sdi, sen , xen, pdn , xdrven, and xtalen. 4. for pins sdo and xout. 5. for pins diag1 and diag2.
aero+ 6 rev. 1.3 figure 1. sclk timing diagram figure 2. pdn timing diagram table 4. ac characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk cycle time t clk figure 1, figure 3 35 ? ? ns sclk rise time t r figure 1, figure 3 ? ? 50 ns sclk fall time t f figure 1, figure 3 ? ? 50 ns sclk high time t hi figure 1, figure 3 10 ? ? ns sclk low time t lo figure 1, figure 3 10 ? ? ns pdn rise time t pr figure 2 ? ? 10 ns pdn fall time t pf figure 2 ? ? 10 ns sdi setup time to sclk t su figure 3 15 ? ? ns sdi hold time from sclk t hold figure 3 10 ? ? ns sen to sclk delay time t en1 figure 3 10 ? ? ns sclk to sen delay time t en2 figure 3, figure 4 12 ? ? ns sen to sclk delay time t en3 figure 3, figure 4 12 ? ? ns sen pulse width t w figure 3, figure 4 10 ? ? ns sclk to sdo time t ca figure 4 ? ? 27 ns digital input pin capacitance 1 ?? 5 pf allowable board capacitance 2 ?? 1 pf notes: 1. for pins sclk, sdi, sen , xen, pdn , xdrven, and xtalen. 2. for pins ckn, ckp, ion, and iop. sclk 80% 20% 50% t r t f t lo t clk t hi pdn 80% 20% t pr t pf
aero+ rev. 1.3 7 figure 3. serial interface write timing diagram figure 4. serial interface read timing diagram t en1 80% 50% 20% 80% 50% 20% 80% 50% 20% d17 d16 a0 t r t w t en2 t f t lo t hi t clk t hold t su sdi sclk sen t en3 80% 50% 20% 80% 50% 20% 80% 50% 20% a0 80% 50% 20% sdi sclk sen sdo od17 od0 od16 t ca t en2 t en3 t w
aero+ 8 rev. 1.3 table 5. receiver characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit gsm input frequency 1 f in gsm 850 band 869 ? 894 mhz e-gsm 900 band 925 ? 960 mhz dcs or pcs input frequency 1 dcs 1800 band 1805 ? 1880 mhz pcs 1900 band 1930 ? 1990 mhz noise figure at 25 c 2,3 nf 25 gsm 850 band ? 2.6 3.3 db e-gsm 900 band ? 2.7 3.4 db dcs 1800 band ? 3.2 3.9 db pcs 1900 band ? 3.6 4.3 db noise figure at 75 c 2,3 nf 75 gsm 850 band ? 3.3 4.0 db e-gsm 900 band ? 3.4 4.1 db dcs 1800 band ? 4.1 4.8 db pcs 1900 band ? 4.8 5.5 db noise figure at 85 c 2,3 nf 85 gsm 850 band ? 3.4 4.1 db e-gsm 900 band ? 3.5 4.2 db dcs 1800 band ? 4.5 5.2 db pcs 1900 band ? 5.1 5.8 db 3 mhz input desensitization 2,3,4 des 3 gsm input ?25 ?21 ? dbm dcs/pcs inputs ?28 ?25 ? dbm 20 mhz input desensitization 2,3,4 des 20 gsm input ?20 ?16 ? dbm dcs/pcs inputs ?19 ?15 ? dbm input ip2 2 ip2 |f 1,2 ? f 0 | 6 mhz, |f 2 ? f 1 | = 100 khz 29 40 ? dbm input ip3 2 ip3 |f 2 ? f 1 | 800 khz, f 0 =2f 1 ? f 2 ?18 ?12 ? dbm image rejection 2,4 ir gsm input 28 35 ? db dcs/pcs inputs 28 40 ? db 1 db input compression 2,5 cp max gsm input ?28 ?23 ? dbm dcs/pcs inputs ?27 ?22 ? dbm 1 db input compression 2,6 cp min gsm input ?23 ?18 ? dbm dcs/pcs inputs ?23 ?18 ? dbm minimum voltage gain 2,6,7 g min gsm input 4.5 8.5 12.5 db dcs/pcs inputs 11.5 15.5 19.5 db maximum voltage gain 2,7 g max gsm input 100 104 108 db dcs/pcs inputs 96 102 106 db lna voltage gain 3,8 g lna gsm input ? 17 ? db dcs/pcs inputs ? 15 ? db
aero+ rev. 1.3 9 lna gain control range g lna gsm input 131721db dcs/pcs inputs 4 8 12 db analog pga control range g apga 13 16 19 db analog pga step size 3.2 4.0 4.8 db digital pga control range g dpga ?63?db digital pga step size ? 1 ? db maximum differentia l output voltage 9 dacfs[1:0] = 00 0.8 1.0 1.2 v ppd dacfs[1:0] = 01 1.6 2.0 2.4 v ppd dacfs[1:0] = 10 2.8 3.5 4.2 v ppd output common mode voltage 9 daccm[1:0] = 00 0.8 1.0 1.2 v daccm[1:0] = 01 1.05 1.25 1.45 v daccm[1:0] = 10 1.15 1.35 1.55 v differential output offset voltage 9,10 ??50mv baseband gain error 9,10 ?? 1 % baseband phase error 9,10 ?? 1deg output load resistance 9 r l single-ended 10 ? ? k output load capacitance 9 c l single-ended ? ? 10 pf group delay 11 csel = 0 ? ? 22 s csel = 1 ? ? 16 s differential group delay 11 csel = 0 ? ? 1.5 s csel = 1 ? ? 1 s powerup settling time 3,12 from powerdown ? 200 220 s notes: 1. gsm input pins rfigp and rfign. dcs input pins rfidp and rfidn. pcs input pins rfipp and rfipn. on the si4200db, the pcs input should be used for either pcs 1900 or dcs 1800 bands. 2. measurement is performed with a 2:1 balun (50 input, 200 balanced output) and includes matching network and pcb losses. measured at max gain (again[2:0] =100b, lnag[1:0] = 01b, lnac[1:0] = 01b) unless otherwise noted. noise figure measurements are referred to 290 k. insertion loss of the balun is removed. 3. specifications guaranteed by characterization. 4. input signal at balun is ?102 dbm. snr at baseband output is 9 db. 5. again[2:0]=000b, lnag[1:0] = 01b, lnac[1:0] = 01b. 6. again[2:0]=000b, lnag[1:0] = 00b, lnac[1:0] = 00b. 7. voltage gain is defined as the differential rms voltage at the rxip /rxin pins or rxqp/rxqn pins divided by the rms voltage at t he balun input with dacfs[1:0] = 01 and csel = 1. gain is 1.5 db hi gher with csel = 0. minimum and maximum values do not include the variation in the si4201 dac full scale voltage (also see maximum differential output voltage specification). 8. voltage gain is defined as the differential rms voltage at t he lna output divided by the rms voltage at the balun output. 9. output pins rxip, rxin, rxqp, rxqn. 10. the baseband signal path is entirely digita l. gain, phase, and offset errors at the baseband outputs are because of the si4201 d/a converters. offsets can be measured and calibrated ou t. see zerodel[2:0] in the register description. 11. group delay is measured from antenna input to baseband outputs. differential group delay is measured in-band. 12. includes settling time of the si4134t frequency synthesizer with 13 mhz dcxo output settled. settling to 5 degrees phase error measured at rxip, rxin, rxqp, and rxqn pins. table 5. receiver characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero+ 10 rev. 1.3 figure 5. receive path magnitude response (csel = 0) figure 6. receive path passband magnitude response (csel = 0) figure 7. receive path passband group delay (csel = 0) 0 50 100 150 200 250 300 350 400 ?120 ?100 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 0) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 0) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 15 16 17 18 19 20 21 22 23 24 25 receive path passband group delay (csel = 0) group delay (usec) frequency (khz)
aero+ rev. 1.3 11 figure 8. receive path magnitude response (csel = 1) figure 9. receive path passband magnitude response (csel = 1) figure 10. receive path passband group delay (csel = 1) 0 50 100 150 200 250 300 350 400 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 1) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 1) magnitude (db) frequency (khz) 0 10 20 30 40 50 60 70 80 90 10 0 10 11 12 13 14 15 16 17 18 19 20 receive path passband group delay (csel = 1) group delay (usec) frequency (khz)
aero+ 12 rev. 1.3 table 6. transmitter characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rfog output frequency 1 gsm 850 band 824 ? 849 mhz e-gsm 900 band 880 ? 915 mhz rfod output frequency 2 dcs 1800 band 1710 ? 1785 mhz pcs 1900 band 1850 ? 1910 mhz i/q differential input swing 3,4 0.88 ? 2.2 v ppd i/q input common-mode 3 1.1 ? 1.4 v i/q differential input resistance 3,4 bbg[1:0] = 11b 26 30 35 k bbg[1:0] = 00b 22 25 29 k bbg[1:0] = 01b 17 20 23 k powered down ? hi-z ? k i/q input capacitance 3,5 ?? 5 pf i/q input bias current 3 13 16 19 a sideband suppression 67.7 khz sinusoid ? ?46 ?34 dbc carrier suppression 67.7 k hz sinusoid ? ?48 ?33 dbc im3 suppression 67.7 khz sinusoid ? ?57 ?50 dbc phase error 5 ?1.93.0 o rms ?510 o peak txvco pushing 1,2 open loop ? 100 ? khz/v txvco pulling 1,2 vswr 2:1, all phases open loop ?200?khz pp rfog output modulation spectrum 1,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?68 dbc rfod output modulation spectrum 2,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?65 dbc rfog output phase noise 1,5,7 10 mhz offset ? ?160 ?155 dbc/hz 20 mhz offset ? ?166 ?164 dbc/hz rfod output phase noise 2,5,7 20 mhz offset ? ?163 ?157 dbc/hz rfog output power level 1 z l =50 7911dbm rfod output power level 2 z l =50 6810dbm
aero+ rev. 1.3 13 rf output harmonic suppression 1,2 2nd harmonic ? ? ?20 dbc 3rd harmonic ? ? ?10 dbc powerup settling time 5,8 from powerdown ? ? 150 s notes: 1. measured at rfog pin. 2. measured at rfod pin. 3. input pins txip, txin, txqp, and txqn. 4. differential input swing is programmable with the bbg[1:0] bi ts in register 04h. program these bits to the closest appropriate value. the i/q input resistance scales inversely with the bbg[1:0] setting. 5. specifications are guaran teed by characterization. 6. measured with pseudo-random pattern. carrier power and noise power < 1.8 mhz measured with 30 khz rbw. noise power 1.8 mhz measured with 100 khz rbw. 7. measured with all 1s pattern. 8. including settling time of the si4134t frequency synthesizer with 13 mhz dcxo output settl ed. settling time measured at the rfod and rfog pins to 0.1 ppm frequency error. table 6. transmitter characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero+ 14 rev. 1.3 table 7. frequency synthesizer characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rf1 vco frequency 1 f rf1 gsm 850 band 1737.8 ? 1787.8 mhz e-gsm 900 band 1849.8 ? 1919.8 mhz dcs 1800 band 1804.9 ? 1879.9 mhz pcs 1900 band 1929.9 ? 1989.9 mhz rf2 vco frequency 1 f rf2 gsm 850 band 1272 ? 1297 mhz e-gsm 900 1279 ? 1314 mhz dcs 1800 band 1327 ? 1402 mhz pcs 1900 band 1423 ? 1483 mhz if vco frequency 1 f if gsm 850 band ? 896 ? mhz e-gsm 900 band 880?895 mhz 900?915 mhz ?798?mhz e-gsm 900 band 895?900 mhz ?790?mhz dcs 1800 band ? 766 ? mhz pcs 1900 band ? 854 ? mhz rf1 pll phase detector update frequency f gsm input, rfup = 0 ?200?khz dcs/pcs inputs, rfup = 1 ?100?khz if and rf2 pll phase detector update frequency f ?200?khz rf2 vco nominal capacitance 2,3 c nom ?4.8? pf if vco nominal capacitance 2,3 ?6.5? pf rf2 vco package inductance 2,3 l pkg ?2.0?nh if vco package inductance 2,3 ?1.6?nh rf1 vco pushing 3 open loop ? 500 ? khz/v rf2 vco pushing 3 ?400?khz/v if vco pushing 3 ?300?khz/v rf1 vco pulling 3 vswr = 2:1, all phases, open loop ?400?khz pp rf2 vco pulling 3 ?100?khz pp if vco pulling 3 ?100?khz pp rf1 pll phase noise 3 3 mhz offset ? ?144 ?138 dbc/hz rf2 pll phase noise 3 400 khz offset ? ?126 ?121 dbc/hz if pll phase noise 3 400 khz offset ? ?128 ?123 dbc/hz
aero+ rev. 1.3 15 rf1 pll spurious 3 3 mhz offset ? ?95 ?83 dbc rf2 pll spurious 3 400 khz offset ? ?80 ?75 dbc if pll spurious 3 400 khz offset ? ?80 ?70 dbc notes: 1. for the gsm input, the rf1 vco is divided by two on the si 4200. during transmit, the if vco is divided by two on the si4200. these tuning ranges are guarant eed provided the vcos on the si4134t are properly centered during the pc board design phase. see ?an49: aero transceiv er pcb layout guidelines ? for more information. 2. see "4.4. vco inductor design" on page 22. 3. specifications are guaran teed by characterization. table 8. reference oscillator (dcxo) characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit xdrv board capacitance c xdrv ?? 2 pf xtal1 trace capacitance 1 c xtal1 ?0.90? pf xtal2 trace capacitance 1 c xtal2 ?0.63? pf crystal oscillation frequency f ref xsel = 0, div2 = 0 ? 13 ? mhz xsel = 1, div2 = 1 ? 26 ? mhz crystal load capacitance c l ?8?pf crystal sensitivity 2 s ? 22.5 ? ppm/pf initial crystal frequency offset f off t a =25c ?10 ? 10 ppm crystal frequency tolerance 3 f tol ?10 ? 10 ppm cdac range 4 f cdac 20 ? ? ppm cdac step size 4,5 ?1.01.5ppm cvar input voltage v xafc 0?2.5v cvar range 4 f cvar v ctl = 0 to 2.5 v 20 30 60 ppm powerup settling time t dcxo v ctl = 1.25 v ? 1.0 ? ms notes: 1. see ?an49: aero transceiver pcb layout guidelines? for suggested layout. 2. allowable manufacturing tolerance of 10% from typical value . 3. crystal accuracy over temperature range. 4. specifications guaranteed when usin g a crystal that conforms to f ref =13mhz, c l = 8 pf, s = 22.5 ppm/pf, f off = 10 ppm, and f tol = 10 ppm. 5. average step size over cdac codes 0 to 63. table 7. frequency synthesizer characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
aero+ 16 rev. 1.3 2. typical triple-band application schematic notes: 1. connect gnd pad on bottom of u1?u3 to gnd. 2. all v dd pins may be fed from a single supply or regulator. 3. for dual-band designs, the dcs lna input pins (u1 pins 19?20) should be grounded. for a complete pinout, see "7. pin descriptions: si4200db-bm" on page 39. 4. see ?an49: aero transceiver pcb layout guidelines? for details on the following: lna matching network (c1?c6, l1?l3). values should be custom tuned for a specific pcb layout and saw filter to optimize performance. differential traces between the saw filter s (z1?z3) and transceiver (u1) pins 17?22. detailed saw filter (z1?z3) requirements. l4 and pcb inductor trace l5 for frequency synthesizer (u3) pins 1?2 and 20?21. ckp/ckn and iop/ion differential traces between transceiv er (u1) pins 1?4 and baseband interface (u2) pins 9?12. x1 connection to u3 pins 11?12. 5. xen, xdrven, and xtalen are recommended to be tied together and controlled simultaneously. vdd vdd vdd vdd vdd vdd vdd vdd vdd pdn sen sclk sdi txip sdo rxqn rxip rxin rxqp egsm tx output dcs/pcs tx ou tput txin txqp txqn egsm rx input dcs rx input pcs rx input xafc xtal_en z1 out- out+ in gnd c7 c3 c4 u2 si4201 gnd 1 rxqp 2 rxqn 3 rxip 4 rxin 5 vdd 6 xin 7 ckp 9 ckn 10 iop 11 sdo 15 pdn 14 xoe 13 ion 12 gnd 8 sen 16 sclk 17 sdi 18 xout 19 vdd 20 c12 c5 c13 c6 13/26mhz l2 c14 c1 c10 l4 c2 l3 c9 u1 si4200 l2 28 txqp 7 ckn 3 ckp 4 txip 5 txin 6 txqn 8 iflop 9 iflon 10 rflop 12 rflon 13 vdd 14 diag2 15 rfidn 20 rfidp 19 rfipn 18 rfipp 17 diag1 16 rfign 22 rfigp 21 rfog 25 rfod 24 vdd 23 gnd 11 gnd 27 vdd 26 ion 1 iop 2 l1 29 gnd 30 pdn 31 vdd 32 z2 out- out+ in gnd l5 pcb trace l1 u3 si4134t gnd 6 iflb 1 ifla 2 gnd 32 vdd 7 pdn 3 sdo 18 sen 15 sclk 16 sdi 17 gnd 19 rfld 20 rflc 21 gnd 24 nc 23 gnd 22 gnd 25 rflon 26 rflop 27 vdd 28 iflon 29 iflop 30 vdd 31 xdrven 4 xdrv 5 gnd 8 nc 9 nc 10 xtal1 11 xtal2 12 xtalen 13 xafc 14 z3 out- out+ in gnd c11 x1
aero+ rev. 1.3 17 3. bill of materials component(s) value/description supplier(s) c1?c2 1.2 pf, 0.1 pf, c0g (gsm 850 and e-gsm 900) murata grm36c0g series venkel c0402c0g500 series c3?c4 1.0 pf, 0.1 pf, c0g (dcs 1800) murata grm36c0g series venkel c0402c0g500 series c5?c6 1.0 pf, 0.1 pf, c0g (pcs 1900) murata grm36c0g series venkel c0402c0g500 series c7 100pf, 5%, c0g venkel c0402c0g500 series c9?c10, c13?c14 22 nf, 20%, z5u c11?c12 10 pf, 20%, c0g l1 24 nh, 5% murata lqw18an series (0603 size) murata lqw15a series (0402 size) l2 7.5 nh, 0.5 nh murata lqw18an series (0603 size) murata lqw15a series (0402 size) l3 6.8 nh, 0.2 nh murata lqw18an series (0603 size) murata lqw15a series (0402 size) l4 3.9 nh, 5% multi-layer (0402 or 0603 size) l5 inductor for rf2 vco pcb trace r1 100 , 5% u1 gsm transceiver silicon laboratories si4200-bm u2 universal baseband interface s ilicon laboratories si4201-bm u3 rf synthesizer silicon laboratori es si4134t-bm x1 13 or 26 mhz crystal, c l =8.0pf kds br13000aa0e kss cx96fffbqaj13 z1 gsm 850 rx saw filter (150 or 200 balanced output) epcos b39881-b7719-c610 (6-pin, 2.0x2.5 mm) epcos b39881-b9001-c710 (5-pin, 1.4x2.0 mm) murata safsd881mfl0t00r00 (6-pin, 2.0x2.5 mm) murata safek881mfl0t00r00 (6-pin, 1.6x2.0 mm) e-gsm 900 rx saw filter (150 or 200 balanced output) epcos b39941-b7721-c910 (6-pin, 2.0x2.5 mm) epcos b39941-b7820-c710 (5-pin, 1.4x2.0 mm) murata safsd942mfm0t00r00 (6-pin, 2.0x2.5 mm) murata safek942mfm0t00r00 (6-pin, 1.6x2.0 mm) z2 dcs 1800 rx saw filter (150 or 200 balanced output) epcos b39182-b7749-c910 (6-pin, 2.0x2.5 mm) epcos b39182-b7821-c710 (5-pin, 1.4x2.0 mm) murata safsd1g84fa0t00r00 (6-pin, 2.0x2.5 mm) murata safek1g84fa0t00r00 (6-pin, 1.6x2.0 mm) z3 pcs 1900 rx saw filter (150 or 200 balanced output) epcos b39202-b7741-c910 (6-pin, 2.0x2.5 mm) epcos b39202-b7825-c710 (5-pin, 1.4x2.0 mm) murata safsd1g96fb0t00r00 (6-pin, 2.0x2.5 mm) murata safek1g96fa0t00r00 (6-pin, 1.6x2.0 mm)
aero+ 18 rev. 1.3 4. functional description figure 11. aero+ transceiver block diagram the aero+ transceiver is the industry?s most integrated rf front end for multi-band gsm/gprs digital cellular handsets and wireless data modems. the chipset consists of the si4200 gsm transceiver, si4201 universal baseband interface, and si4134t dual rf synthesizer with an integrated digitally-controlled crystal oscillator (dcxo). the high ly integrated solution eliminates the if saw f ilter, external low noise amplifiers (lnas) for three bands, transmit and rf voltage-controlled oscillato r (vco) modules, and more than 60 other discrete components found in conventional designs. the high level of integration combined with quad flat no- lead package (qfn) technology and fine line cmos process technology results in a solution with 50% less area and 80% fewer components than competing solutions. a triple-band gsm transceiver using the aero+ chipset can be implemented with 19 components in less than 2 cm 2 of board area. this level of integration is an enabling force in lowering the cost, simplifying the design and manufacturing, and shrinking the form factor in next-g eneration gsm/gprs voice and data terminals. the receive section uses a digital low-if architecture that avoids the difficulti es associated with direct conversion while deliveri ng lower solution cost and reduced complexity. the universal baseband interface is compatible with any supplier?s baseband subsystem. the transmit section is a complete up-conversion path from the baseband subsystem to the power amplifier, and uses an offset phase-locked loop (pll) with a fully integrated transmit vco. the frequency synthesizer uses silicon laboratories? proven technology that includes integrated rf and if vcos, varactors, and loop filters. the unique integer-n pll architecture used in the si4134t produces a transient response superior in speed to fractional-n architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. this fast transient response makes the aero+ chipset well suited to gprs multi-slot applications where channel switching and settling times are critical. while conventional solutions use bicmos or other bipolar process technologies, the aero+ chipset is the industry?s first cellular tran sceiver to be implemented in a 100% cmos process. this brings the cost savings and extensive manufacturing capacity of cmos to the gsm market. adc adc pga pga lna lna lna si4200 if pll rf pll si4134t gsm dcs pcs gsm dcs pcs dcxo 0 / 90 antenna switch det baseband dac dac pga pga channel filter 100 khz si4201 i q i q pa pa afc xout
aero+ rev. 1.3 19 4.1. receive section figure 12. receiver block diagram the aero+ transceiver uses a low-if receiver architecture that allows for the on-chip integration of the channel selection filters, eliminating the external rf image reject filters and the if saw filter required in conventional superheterodyne architectures. compared to a direct-conversion architecture, the low-if architecture has a much greater degree of immunity to dc offsets that can arise from rf local oscillator (rflo) self-mixing, 2nd-order distortion of blockers, and device 1/f noise. this relaxes the common-mode balance requirements on the input saw filters and simplifies pc board design and manufacturing. the si4200 integrates three differential-input lnas. the gsm input supports the gsm 850 (869?894 mhz) or e- gsm 900 (925?960 mhz) bands. the dcs input supports the dcs 1800 (1805?1880 mhz) band. the pcs input supports the pcs 1900 (1930?1990 mhz) band. for quad-band designs, saw filters for the gsm 850 and e-gsm 900 bands should be connected to a balanced combiner which drives the gsm input for both bands. for dual-band designs using the si4200db-bm, the pcs input should be used for either dcs 1800 or pcs 1900 bands. the lna inputs are matched to the 200 balanced- output saw filters throug h external lc matching networks. see ?an49: aero transceiver pcb layout guidelines? for details. the lna gain is controlled with the lnag[1:0] and lnac[1:0] bits in register 05h. a quadrature image-reject mixer downconverts the rf signal to a 100 khz intermediate frequency (if) with the rflo from the si4134t frequency synthesizer. the rflo frequency is between 1737.8 and 1989.9 mhz, and is divided by two in the si4200 for gsm 850 and e- gsm 900 modes. the mixer output is amplified with an analog programmable gain amplifier (pga), which is controlled with the again[2:0] bits in register 05h. the quadrature if signal is digitized with high resolution a/d converters (adcs). the si4201 downconverts the adc output to baseband with a digital 100 khz quadrature lo signal. digital decimation and iir filters perform channel selection to remove blocking and reference interference signals. the response of the iir filter is programmable to a high selectivity setting (csel = 0) or a low selectivity setting (csel = 1). the low selectivit y filter has a flatter group delay response that may be desirable where the final channelization filter is in the baseband chip. after channel selection, the digital output is scaled with a digital pga, which is contro lled with the dgain[5:0] bits in register 05h. the lnag[1:0], lnac[1:0], again[2:0] and dgain[5:0] bits must be set to provide a constant amplitude signal to the baseband receive inputs. see ?an51: aero transceiver agc strategy? for more details. dacs drive a differential analog signal onto the rxip, rxin, rxqp, and rxqn pins to interface to standard analog-input baseband ics. no special processing is required in the baseband for offset compensation or extended dynamic range. the receive and transmit baseband i/q pins can be mult iplexed together into a 4- wire interface. the common mode level at the receive i and q outputs is programmable with the daccm[1:0] bits, and the full scale level is programmable with the dacfs[1:0] bits in register 12h. baseband dac dac pga pga channel filter 100 khz adc adc pga pga lna lna lna si4200 0 / 90 si4134t si4201 i q n rf1 [15:0] rfup rxband[1:0] lnac[1:0] lnag[1:0] again[2:0] csel dgain[5:0] daccm[1:0] dacfs[1:0] zerodel[2:0] rf pll pcs dcs gsm
aero+ 20 rev. 1.3 4.2. transmit section figure 13. transmitter block diagram the transmit (tx) section consists of an i/q baseband upconverter, an offset phase-locked loop (opll), and two output buffers that can drive external power amplifiers (pa): one for the gsm 850 (824 to 849 mhz) and e-gsm 900 (880 to 915 mhz) bands and one for the dcs 1800 (1710 to 1785 mhz) and pcs 1900 (1850 to 1910 mhz) bands. the opll requires no external filtering to attenuate transmitter noise or spurious signals in the receive band, saving both cost and power. additionally, the output of the transmit vco (txvco) is a constant-envelope signal that reduces the problem of spectral spreading caused by non-linearity in the pa. a quadrature mixer upconverts the differential in-phase (txip, txin) and quadrature (txqp, txqn) signals with the iflo to generate a ssb if signal that is filtered and used as the reference input to the opll. the si4134t generates the iflo frequency between 766 and 896 mhz. the iflo is divided by two to generate the quadrature lo signals for the quadrature modulator, resulting in an if between 383 and 448 mhz. for the e- gsm 900 band, two different iflo frequencies are required for spur management. therefore, the if pll must be programmed per channel in the e-gsm 900 band. the iflo frequencies are defined in table 6 on page 12. the opll consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated txvco. the txvco is centered between the dcs 1800 and pcs 1900 bands, and its output is divided by two for the gsm 850 and e-gsm 900 bands. the si4134t generates the rflo frequency between 1272 and 1483 mhz. to allow a single vco to be used for the rflo, high-side injection is used for the gsm 850 and e-gsm 900 bands, and low-si de injection is used for the dcs 1800 and pcs 1900 bands. the i and q signals are automatically swapped within the si4200 when switching bands. additionally, the swap bit in register 03h can be used to manually exchange the i and q signals. low-pass filters before the opll phase detector reduce the harmonic content of the quadrature modulator and feedback mixer outputs. the cutoff frequency of the filters is programmable with the fif[3:0] bits in register 04h and should be set to the recommended settings detailed in the register description. baseband det pa pa i q gsm dcs/pcs if pll rf pll si4134t 2 fif[3:0] n rf2 [15:0] pdrb n if [15:0] pdib 1, 2 txband[1:0] si4200 reg reg bbg[1:0] swap
aero+ rev. 1.3 21 4.3. frequency synthesizer figure 14. si4134t frequency synthesizer block diagram the si4134t dual frequency synthesizer is a monolithic cmos integrated circuit that performs if and rf synthesis. an integrated digitally-controlled crystal oscillator (dcxo) is provided to generate the reference clock. the dcxo allows the use of a standard crystal resonator, avoiding the n eed for a crystal oscillator module. two complete plls are integrated including vcos, varactors, resonators, loop filters, reference and vco dividers, and phase detectors. differential outputs for the if and rf plls are provided for direct connection to the si4200 transceiver ic. the rf pll uses two multiplexed vcos. the rf1 vco is used for receive mode, and the rf2 vco is used for transmit mode. the if pll is used only during transmit mode and uses a single vco. the if and rf output frequencies are set by programming the n-divider registers, n rf1 , n rf2 , and n if . programming the n-divider register for either rf1 or rf2 automatically selects the proper vco. the output frequency of each pll is as follows: a programmable divider in the input stage allows either a 13 or 26 mhz reference frequency depending on the choice of crystal. when configured for 26 mhz operation using a tcxo, the div2 bit in register 31h should be set appropriately. the rf pll phase detector update rate (f ) can be programmed with the rfup bit in register 31h to either f = 100 khz or f = 200 khz. receive mode should use f = 100 khz in dcs 1800 and pcs 1900 bands, and f = 200 khz in the gsm 850 and e-gsm 900 bands. for transmit modes, the rf2 and if pll phase detector update rates should always be configured for f = 200 khz. si4134t self tune det rf1 rf2 n n rf 1 [15:0] n rf 2 [15:0] 1,2 power control serial i/o n det n if [15:0] div2 pdib pdrb sdosel[3:0] if pll rf pll self tune rfld iflb ifla rflop sen sclk sdo sdi pdn xafc dcxo 65, 130 rfup cdac[5:0] xdrven xdrv xtalen xtal1 xtal2 rflc rflon iflop iflon f out nf =
aero+ 22 rev. 1.3 4.4. vco inductor design figure 15. vco block diagram 4.4.1. determining l ext the center frequencies for the rf2, and if vcos in the si4134t are set using an external inductance (l ext ). it is very important that l ext be properly designed to ensure maximum manufacturing margin for the desired vco frequency tuning ranges. because the total tank inductance is in the low nh range, the inductance of the package (l pkg ) must be considered in determining the correct external inductance. figure 15 shows the detailed configuration of the integrated vcos. the total inductance (l tot ) of each vco is the sum of the external inductance (l ext ) and the package inductance (l pkg ). the total capacitance (c tot ) of each vco is the sum of the self tuning capacitance (c tune ), the pll varactor capacitance (c var ), and the fixed capacitance (c fix ). the nominal capacitance (c nom ) of each vco is calculated with c tune and c var at their center values. c nom and l pkg values are defined in table 7 on page 14. the center frequency is calculated as follows: the value for the external inductor is determined by the following: where f cen = desired center frequency of vco. c nom = nominal capacitance from table 7. l pkg = package inductance from table 7. l ext = external inductance required. for example, the rf2 vco for a triple-band design requires f cen = 1381 mhz. table 7 on page 14 shows c nom = 4.8 pf and l pkg = 2.02 nh for the rf2 vco. the previous equation shows l ext = 0.75 nh should be connected between the rflc and rfld pins. see ?an49: aero transceiver pcb layout guidelines? for details on how to implement and verify the proper value of l ext . package board ic pll self tune amp c var c tune c fix l ext l pkg /2 l pkg /2 si4134t f cen 1 2 c nom l pkg l ext + () ------------------------------------------------------------------- = l ext 1 2 f cen () 2 c nom ------------------------------------------- - l pkg ? = table 9. vco f cen values (mhz) supported bands rf1* vco rf2 vco if vco european dual-band (900/1800) 1862 1341 782 triple-band (900/1800/1900) 1897 1381 810 quad-band (850/900/1800/1900) or north american dual band (850/1900) 1864 1378 831 *note: l ext is set internally. table 10. vco l ext values (nh) supported bands rf2 vco if vco european dual-band (900/1800) 0.91 4.77 triple-band (900/1800/1900) 0.75 4.34 quad-band (850/900/1800/1900) or north american dual band (850/1900) 0.76 4.04
aero+ rev. 1.3 23 4.5. dcxo overview the si4134t integrates the dcxo circuitry required to generate a precise system reference clock using only an external crystal resonator. (see figure 16.) an internal digitally programma ble capacitor array (cdac) provides a coarse method of adjusting the reference frequency in discrete steps. an integrated analog varactor (cvar) allows for a fine and continuous adjustment of the reference frequency by an external control voltage (xafc). this control voltage is supplied by the afc dac on the baseband ic. the complete dcxo solution effectively replaces the tcvcxo module typically required to provide a 13 or 26 mhz reference clock for the system. the si4134t generates a single-ended 13 or 26 mhz output (xdrv) to drive the si4201, and the si4201 then buffers a 13 or 26 mhz reference clock (xout) to be sent to other system components such as the baseband. the complete circuit is shown in the "2. typical triple-band application schematic" on page 16. 4.5.1. dcxo tuning the dcxo uses the cdac and the cvar to correct for both static and dynamic frequency errors, respectively. to compensate for crystal systematic offset error, the cdac ensures a minimum of 10 ppm frequency adjustment capability. the cdac is programmed using register 28h. the cdac[5:0] register (register 28) may be programmed during powerup or after an initial calibration. periodic adjustments to compensate for aging may also be performed over time to ensure accuracy. the baseband determines the appropriate frequency adjustment based on the receipt of the fcch burst. the baseband then adjusts the xafc voltage using the baseband afc dac (12 or 13-bit), which controls the varactor on the si4134t. the baseband afc dac can ad just cvar to correct for frequency variations caused by temperature drift. the step size per bit depends on the resolution of the afc dac and its output voltage range. 4.5.2. dcxo crystal selection the tuning range specifications listed in table 8 on page 15 for cdac and cvar assume that aero+ is used with a crystal that conforms to the crystal parameters listed in the same table. other crystals may be used with aero+ for cost and/or performance reasons. for example, using a higher sensitivity crystal extends the cvar and the cdac frequency compensation range. howeve r, care must be taken when using a more sensitive crystal because other system parameters are affected. contact silicon laboratories' applications support for assistance in specifying other crystals. figure 16. dcxo system signal routing diagram 4.6. serial interface a three-wire serial interfac e is provided to allow an external system controller to write the control registers for dividers, receive path gain, powerdown settings, and other controls. the serial control word is 24 bits in length, comprised of an 18-b it data field and a 6-bit address field as shown in figure 17. a single logical register space is shared among the three chips, which is summarized in table 11 on page 25. figure 17. serial interface format baseband xtal1 xtal2 si4134t xdrv xafc to plls cdac[5:0] afc dac si4201 xout xin y1 cvar amp d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 5 a 4 a 3 a 2 a 1 a 0 data field address field last bit clocked in d 16 d 17
aero+ 24 rev. 1.3 the serial interface pins are intended to be connected in parallel to both the si4201 and the si4134t. serial control is relayed from the si4201 to the si4200 over the signal interface (iop/ion and ckp/ckn pins). all registers must be written when the pdn pin is asserted (low), except for register 22h. all serial interface pins should be held at a constant level during receive and transmit bursts to minimize spurious emissions. this includes stopping the sclk clock. a timing diagram for the serial interface is shown in figure 3 on page 7. when the serial interface is enabled (i.e., when sen is low), data and address bits on the sdi pin are clocked into an internal shift register on the rising edge of sclk. data in the shift register is then transferred on the rising edge of sen into the internal data register addressed in the address field. the internal shift register ignores any leading bits before the 24 required bits. the serial interface is disabled when sen is high. optionally, registers can be read as illustrated in figure 4 on page 7. the serial output data appears on the sdo pin after writing the revision register with the address to be read. sdo is enabled when pdn =0 on the si4201 and when pdn = 1 on the si4134t, allowing the sdo pin to be shared. writing to any of the registers causes the function of sdo to revert to its previously programmed function. 4.7. xdrv buffer to supply a frequency adjusted reference clock to the si4201, the xdrven pin on th e si4134t must be high. when held low, the si4134t is fully operational, but no reference signal (either 13 or 26 mhz) is sourced from the xdrv pin. the xtalen signal controls the powerup state of the dcxo and must be enabled (xtalen = 1) before the xdrv signal can be sourced. 4.8. xout buffer the si4201 contains a reference clock buffer to drive the baseband input. the clock signal from the si4134t is capacitively coupled to the xin pin on the si4201. to achieve complete powerdown during sleep, the xen pin must be set low, the xbuf bit in register 12 must be set to 0, and the xpd1 bit in register 11 must be set to 1. during normal operation, these bits should set to their default values. the xout buffer is a cmos driver stage with approximately 250 of series resistance. this buffer is enabled when the xen hardware control (pin 13 on the si4201) is set high, independent of the pdn control pin.
aero+ rev. 1.3 25 5. control registers notes: 1. any register not listed here is reserved and should not be written. writing to reserved register s may result in unpredictable behavior. 2. master registers 20h to 24h simplify programming the aero+ tran sceiver to support initiation of receive (rx) and transmit (tx) operations with only two register writes. 3. see ?an50: aero transceiver programming guide? for detailed instructions on register programming. table 11. register summary reg name bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00h si4200 revision/read 0000000000 rev0[7:0] 01h reset 00000000000000000r eset 02h mode 000000000000000automode[1:0] 03h config 0 0 0 0 diag[1:0] swap 0 0 0 txband[1:0] rxband[1:0] 0 0 1 0 04htransmit 00000001bbg[1:0] fif[3:0] 000 0 05h receive 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] 10h si4201 revision/read 0000000000 rev1[7:0] 11h config 0000 dpds[2:0] xpd11xsel0101000csel 12hdac config00000001xbuf?0zdbszerodel[2:0]daccm[1:0]dacfs[1:0] 19hreserved 00000000000000000 0 master registers 20h rx master #1 rxband[1:0] n rf1 [15:0] 21h rx master #2 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] 22hrx master #3000000000000 dgain[5:0] 23h tx master #1 txband[1:0] n rf2 [15:0] 24h tx master #2 fif[3:0] n if [13:0] 28h cdac 000000000000 cdac[5:0] 30h si4134t revision/read 0000000000 rev3[7:0] 31h config 000 sdosel[3:0] 000000rfupdiv200 0 32hpowerdown0000000000000000pdibpdrb 33h rf1 n divider 0 0 n rf1 [15:0] 34h rf2 n divider 0 0 n rf2 [15:0] 35h if n divider 0 0 n if [15:0]
aero+ 26 rev. 1.3 note: registers on the si4200 can be read by writing this r egister with the address of the register to be read. register 00h. revision/read (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev0[7:0] bit name function 17:8 reserved read as zero. 7:0 rev0[7:0] si4200 revision (read only). 00h = si4200 revision a 01h = si4200 revision b 02h = si4200 revision c 03h = si4200 revision d 14h = si4200db revision e (dual-band) 05h = si4200 revision f (triple-band) register 01h. reset (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name 00000000000000000r eset bit name function 17:1 reserved program to zero. 0 reset chip reset. 0 = normal operation (default). 1 = reset all registers to default values. note: see ?5. control registers? on page 25. for more details. this register must be written to 0 twice after a reset operation. this bit does not reset si4134t registers 30h to 35h.
aero+ rev. 1.3 27 note: calibration must be performed each time the power suppl y is applied. to initiate the calibration mode, set mode[1:0] = 10, and pulse the pdn pin high for at least 150 s. register 02h. mode control (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000000automode[1:0] bit name function 17:3 reserved program to zero. 2auto automatic mode select. 0 = manual. mode is controlled by mode[1:0] bits (default). 1 = automatic. last register write to n rf1 implies rx mode; last register write to n rf2 implies tx mode. mode[1:0] bits are ignored. 1:0 mode[1:0] transmit/receive/calibration mode select. 00 = receive mode (default). 01 = transmit mode. 10 = calibration mode. 11 = reserved. note: these bits are valid only when auto = 0.
aero+ 28 rev. 1.3 register 03h. configuration (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000diag[1:0]swap000txband[1:0]rxband[1:0]0010 bit name function 17:14 reserved program to zero. 13:12 diag[1:0] diag1/diag2 ou tput select. diag1 diag2 00 = lowlow (default) 01 = lowhigh 10 = highlow 11 = highhigh note: these pins can be used to control antenna switch functions. these bits must be programmed with the pdn pin is zero. the diag1/diag2 pins are be held at the desired value regardless of the state of the pdn pin. 11 swap transmit i/q swap. 0 = normal (default). 1 = swap i and q for txip, txin, txqp, and txqn pins. 10:8 reserved program to zero. 7:6 txband[1:0] transmit band select. 00 = gsm 850 or e-gsm 900 (default). 01 = dcs 1800. 10 = pcs 1900. 11 = reserved. 5:4 rxband[1:0] receive band select. 00 = gsm input. (default), 01 = dcs input. 10 = pcs input. 11 = reserved. 3:2 reserved program to zero. 1 reserved program to one. 0 reserved program to zero.
aero+ rev. 1.3 29 register 04h. transmit control (si4200) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00000001 bbg[1:0] fif[3:0] 0000 bit name function 17:11 reserved program to zero. 10 reserved program to one. 9:8 bbg[1:0] tx baseband input full scale differential input voltage. 00 = 1.7 v ppd (default). 01 = 1.3 v ppd . 10 = reserved. 11 = 2.0 v ppd . note: refer to table 6 for minimum and maximum values. set this register to the nearest value. 7:4 fif[3:0] tx if filter cutoff frequency. 0110 = use for dcs 1800 band. 0111 = use for gsm 850, e-gsm 900 and pcs 1900 bands. note: use the recommended setting for each band. other settings reserved. 3:0 reserved program to zero.
aero+ 30 rev. 1.3 register 05h. receive gain (si4200/si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] bit name function 17:14 reserved program to zero. 13:8 dgain[5:0] digital pga gain control. 00h=0db (default). 01h=1db. ... 3fh = 63 db. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 7 reserved program to zero. 6:4 again[2:0] analog pga gain control. 000=0db (default). 001=4db. 010=8db. 011 = 12 db. 100 = 16 db. 101 = reserved. 110 = reserved. 111 = reserved. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 3:2 lnac[1:0] lna bias current control. 00 = minimum current (default). 01 = maximum current. 10 = reserved. 11 = reserved. note: program these bits to the same value as same as lnag[1:0] 1:0 lnag[1:0] lna gain control. 00 = minimum gain (default). 01 = maximum gain. 10 = reserved. 11 = reserved. notes: 1. program these bits to the same value as same as lnac[1:0] 2. see ?an51: aero transceiver agc strategy? for details on setting the gain registers.
aero+ rev. 1.3 31 note: registers on the si4201 can be read by writing this r egister with the address of the register to be read. register 10h. revision/read (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev1[7:0] bit name function 17:8 reserved read as zero. 7:0 rev1[7:0] si4201 revision (read only). 00h = rev a. 01h = rev b. 02h = rev c (latest version). register 11h. configuration (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 dpds[2:0] xpd1 1 xsel 0 1 0 1 0 0 0 csel bit name function 17:14 reserved program to zero. 13:11 dpds[2:0] data path delayed start. 111= use for gsm 850 and gsm 900 bands. 011= use for dcs 1800 and pcs 1900 bands (default). note: use the recommended setting for each band. other settings reserved. 10 xpd1 reference buffer powerdown. 0 = reference buffer automatically enabled (default). 1 = reference buffer disabled. note: this bit should be set to 0 during normal operation. to achieve lowest si4201 powerdown current (i pdn1 ), this bit should be set to 1. the xbuf bit in register 12h must also be set appropriately 9 reserved program to one. 8 xsel reference frequency select. 0 = no divider. xin = 13 mhz (default). 1 = divide xin by 2. xin = 26 mhz. note: the internal clock should always be 13 mhz. 7 reserved program to zero. 6 reserved program to one. 5 reserved program to zero. 4 reserved program to one. 3:1 reserved program to zero. 0 csel digital iir coefficient select. 0 = high selectivity filter (default). 1 = low selectivity filter.
aero+ 32 rev. 1.3 register 12h. dac configuration (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 0 0 0 0 0 0 1 xbuf 0 zdbs zerodel[2:0] daccm[1:0] dacfs[1:0] bit name function 17:11 reserved program to zero. 10 reserved program to one. 9 xbuf reference buffer power control. 0 = reference buffer disabled. 1 = reference buffer automatically enabled (default). note: this bit should be set to 1 during normal operation. to achieve the lowest si4201 power down current (i pdn1 ), this bit should be set to 0. the xpd1 bit in register 12h must also be set appropriately. 8 reserved program to zero. 7zdbs zerodel band select. 0 = use zerodel[2:0] settings co rresponding to dcs/pcs column (default). 1 = use rxband[1:0] to determine ze rodel[2:0] dela y setting (gsm or dcs/pcs). 6:4 zerodel[2:0] rx output zero delay. code gsm dcs/pcs 000: 90 s 130 s(default) 001: 110 s150 s 010: 130 s170 s 011: 140 s180 s 100: 150 s190 s 101: 160 s200 s 110: 180 s220 s 111: reserved note: dac input is forced to zero after pdn is deasserted. this feature can be used for baseband adc offset calibration. offsets induced on channels due to 13 mhz harmonics are not included in the calibrated value. 3:2 daccm[1:0] rx output common mode voltage. 00 = 1.0 v. 01 = 1.25 v (default). 10 = 1.35 v. 11 = reserved. 1:0 dacfs[1:0] rx output differential full scale voltage. 00 = 1.0 v ppd . 01 = 2.0 v ppd (default). 10 = 3.5 v ppd . 11 = reserved.
aero+ rev. 1.3 33 notes: 1. see registers 03h and 33h for bit definitions. 2. when this register is written, th e pdib bit automatically sets to 0, the pdrb bi t is set to 1, and the rfup bit is set as a function of rxband[1:0]. note: see registers 05h and 11h for bit definitions. notes: 1. see register 05h for bit definitions. 2. the dgain[5:0] in register 22h ca n be changed without powering down. register 19h. reserved (si4201) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000000000 bit name function 17:0 reserved program to zero. register 20h. rx master #1 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name rxband[1:0] n rf1 [15:0] register 21h. rx master #2 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] register 22h. rx master #3 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000 dgain[5:0]
aero+ 34 rev. 1.3 notes: 1. see registers 03h and 34h for bit definitions. 2. when this register is written, th e pdib bit automatically sets to 1, and the pdrb bit is set to 1. note: see registers 04h and 35h for bit definitions. register 23h. tx master #1 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name txband[1:0] n rf2 [15:0] register 24h. tx master #2 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name fif[3:0] n if [13:0] register 28h. cdac (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000000000000 cdac[5:0] bit name function 17:6 reserved read as zero. 5:0 cdac[5:0] dcxo coarse frequency dac adjustment. 64 steps. see table 8 on page 15 fo r step size. an in crease in cdac results in a lower oscillating freq uency. likewise, a decrease in cdac results in a higher oscillating frequency. 000000 = highest frequency ... 111111 = lowest frequency
aero+ rev. 1.3 35 note: registers on the si4134t can be read by writing this re gister with the address of the register to be read. register 30h. revision/read (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000 rev3[7:0] bit name function 17:8 reserved read as zero. 7:0 rev3[7:0] si4134t revision (read only). c0h = rev a (latest version). register 31h. main configuration (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 000 sdosel[3:0] 000000rfupdiv2000 bit name function 17:15 reserved program to zero. 14:11 sdosel[3:0] sdo output control register. the mux_output table is as follows: 0000 connected to the output shift register (default). 0001 force the output to low. 0010 reference clock. 0011 lock detect (ldetb) signal from phase detectors. 1111 high impedance. notes: 1. sdo is high-impedance when pdn =0. 2. sdo is serial data output when in register read mode. 10:5 reserved program to zero. 4rfup rf pll update rate (rf1 vco only). 0 = 200 khz update rate (receive gsm modes). 1 = 100 khz update rate (receive dcs and pcs modes). note: this bit is set to 1 when register 20h d[17:16] = 01b or 10b (dcs 1800 or pcs 1900 receive modes) and is set to 0 when d[17:16] = 00b or 11b (gsm 850 or gsm 900 modes). 3div2 input clock frequency. 0 = no divider. xin = 13 mhz. 1 = divide xin by 2. xin = 26 mhz. 2:0 reserved program to zero.
aero+ 36 rev. 1.3 register 32h. powerdown (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0000000000000000pdibpdrb bit name function 17:2 reserved program to zero. 1pdib powerdown if pll. 0 = if synthesizer powered down. 1 = if synthesizer powered up when the pdn pin is high. notes: 1. the if pll is only used in transm it mode. powerdown for receive mode. 2. this bit is set to 0 when register 20h is written (receive mode). 3. this bit is set to 1 when register 23h is written (transmit mode). 0 pdrb powerdown rf pll. 0 = rf synthesizer powered down. 1 = rf synthesizer powered up when the pdn pin is high. notes: 1. this bit is set to 1 when register 20h is written (receive mode). 2. this bit is set to 1 when register 23h is written (transmit mode). register 33h. rf1 n divider (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n rf1 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf1 [15:0] n divider for rf pll (rf1 vco). used for receive mode. register 34h. rf2 n divider (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n rf2 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf2 [15:0] n divider for rf pll (rf2 vco). used for transmit mode.
aero+ rev. 1.3 37 register 35h. if n divider (si4134t) bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n if [15:0] bit name function 17:16 reserved program to zero. 15:0 n if [15:0] n divider for if synthesizer. used for transmit mode.
aero+ 38 rev. 1.3 6. pin descriptions: si4200-g-gm pin number(s) name description 1, 2 ion, iop data output to si4201 (differential). 3, 4 ckn, ckp clock input from si4201 (differential). 5, 6 txip, txin transmit i input (differential). 7, 8 txqp, txqn transmit q input (differential). 9, 10 iflop, iflon iflo input from si4133t (differential). 11, 27, 30, gnd pad gnd ground. connect to ground plane on pcb. 12, 13 rflop, rflon rflo input from si4133t (differential). 14, 23, 26, 32 v dd supply voltage. 15, 16 diag2, diag1 d iagnostic output. can be used as digital outputs to control antenna switch functions. 17, 18 rfipp, rfipn pcs lna input (differential). use for pcs 1900 band. 19, 20 rfidp, rfidn dcs ln a input (differential). use for dcs 1800 band. 21, 22 rfigp, rfign gsm lna input (differential). used for gsm 850 or e-gsm 900 bands. 24 rfod dcs and pcs transmit output to power amplifier. used for dcs 1800 and pcs 1900 bands. 25 rfog gsm transmit outp ut to power amplifier. used for gsm 850 and e-gsm 900 bands. 28, 29 nc these pins should be left disconnected. 31 pdn powerdown input (active low). top view gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 v dd pdn gnd nc nc gnd vdd rfog rfidp rfidn rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8
aero+ rev. 1.3 39 7. pin descriptions: si4200db-bm pin number(s) name description 1, 2 ion, iop data output to si4201 (differential). 3, 4 ckn, ckp clock input from si4201 (differential). 5, 6 txip, txin transmit i input (differential). 7, 8 txqp, txqn transmit q input (differential). 9, 10 iflop, iflon iflo input from si4134t (differential). 12, 13 rflop, rflon rflo input from si4134t (differential). 14, 23, 26, 32 v dd supply voltage. 15, 16 diag2, diag1 d iagnostic output. can be used as digital outputs to control antenna switch functions. 17, 18 rfipp, rfipn pcs lna input (differential). use for dcs 1800 or pcs 1900 bands. 21, 22 rfigp, rfign gsm lna input (differential). used for gsm 850 or e-gsm 900 bands. 24 rfod dcs and pcs transmit output to power amplifier. used for dcs 1800 and pcs 1900 bands. 25 rfog gsm transmit outp ut to power amplifier. used for gsm 850 and e-gsm 900 bands. 28, 29 nc these pins should be left disconnected. 31 pdn powerdown input (active low). 11, 19, 20, 27, 30, gnd pad gnd ground. connect to ground plane on pcb. top view gnd pad 1 2 3 25 26 27 28 29 30 31 32 ion iop txqn txqp ckn ckp txin txip iflop iflon gnd rflop rflon vdd diag2 diag1 v dd pdn gnd nc nc gnd vdd rfog rfidp rfidn rfipp rfipn rfigp rfign vdd rfod 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8
aero+ 40 rev. 1.3 8. pin descriptions: si4201-bm pin number(s) name description 2, 3 rxqp, rxqn receive q output (differential). 4, 5 rxip, rxin receive i output (differential). 6, 20 v dd supply voltage. 7 xin reference frequency input from crystal oscillator. 9, 10 ckp, ckn clock output to si4200 (differential). 11, 12 iop, ion data input from si4200 (differential). 13 xen xout pin enable 14 pdn powerdown input (active low). 15 sdo serial data output. 16 sen serial enable input (active low). 17 sclk serial clock input. 18 sdi serial data input. 19 xout clock output to baseband. 1, 8, gnd pad gnd ground. connect to ground plane on pcb. top view gnd pad 1 2 3 16 17 18 19 20 gnd rxqp rxqn rxip rxin vdd xin gnd ckp ckn v dd xout sdi sclk sen iop ion xen pdn sdo 11 12 13 14 15 6 7 8 9 10 4 5
aero+ rev. 1.3 41 9. pin descriptions: si4134t-bm pin number(s) name description 1, 2 iflb, ifla tuning inductor connection for if vco. 3pdn power down inpu t (active low). 4 xdrven xdrv enable. 5 xdrv reference clock output to si4201. 7, 28, 31 v dd supply voltage. 9, 10, 23 nc no connect. 11 xtal1 crystal input. 12 xtal2 crystal output. 13 xtalen crystal enable. 14 xafc baseband afc signal input. 15 sen serial enable input (active low). 16 sclk serial clock input. 17 sdi serial data input. 18 sdo serial data output. 20, 21 rflc, rfld tuning inductor connection for rf2 vco. 26, 27 rflon, rflop rf pll output to si4200 (differential). 29, 30 iflon, iflop if pll output to si4200 (differential). 6, 8, 19, 22, 24, 25, 32, gnd pad gnd ground. connect to ground plane on pcb. top view gnd pad 1 2 3 25 26 27 28 29 30 31 32 iflb ifla gnd vdd pdn xdrven gnd xdrv nc nc xtal1 xtal2 xtalen xafc sen sclk gnd v dd iflop iflon vdd rflop rflon gnd gnd rfld sdi sdo rflc gnd nc gnd 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 4 5 6 7 8
aero+ 42 rev. 1.3 10. ordering guide part number description package type operating temperature si4200-g-gm tri-band transceiver gsm 850 or e-gsm 900, dcs 1800, pcs 1900 qfn pb-free* ?20 to 85 c si4200db-bm dual-band aero transceiver gsm 850/pcs 1900 or e-gsm 900/dcs 1800 qfn* ?20 to 85 c si4200db-gm dual-band aero transceiver gsm 850/pcs 1900 or e-gsm 900/dcs 1800 qfn pb-free* ?20 to 85 c si4201-bm universal baseband interface qfn* ?20 to 85 c si4201-gm universal baseband interface qfn pb-free* ?20 to 85 c si4134t-bm dual rf synthesizer with dcxo qfn* ?20 to 85 c SI4134T-GM dual rf synthesizer with dcxo qfn pb-free* ?20 to 85 c *note: add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel.
aero+ rev. 1.3 43 11. package outline: si4200-g-gm and si4200db-bm figure 18 illustrates the package details for the si4200-g-gm and si4200db-bm. table 12 lists the values for the dimensions shown in the illustration. figure 18. 32-pin quad flat no-lead package (qfn) table 12. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 4.75 bsc a1 0.00 0.01 0.05 d2, e2 3.15 3.30 3.45 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.30 0.40 0.50 d, e 5.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. the package weight is approximately 68 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 32 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 pin1 id 0.50 dia. b 32 b e l pin1 id 0.20 r. e e e1 d d1
aero+ 44 rev. 1.3 12. package outline: si4201-bm figure 19 illustrates the package details for the si4201-bm. table 13 lists the values for the dimensions shown in the illustration. figure 19. 20-pin quad flat no-lead package (qfn) table 13. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 3.75 bsc a1 0.00 0.01 0.05 d2, e2 1.95 2.10 2.25 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.50 0.60 0.75 d, e 4.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. the package weight is approximately 42 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 20 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 e e1 pin1 id 0.50 dia. d b 20 d1 b e e l
aero+ rev. 1.3 45 13. package outline: si4134t-bm figure 18 illustrates the package details for the si4134t-bm. table 12 lists th e values for the dimensions shown in the illustration. figure 20. 32-pin quad flat no-lead package (qfn) table 14. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? 0.85 0.90 d1, e1 4.75 bsc a1 0.00 0.01 0.05 d2, e2 2.95 3.10 3.25 a2 ? 0.65 0.70 e 0.50 bsc a3 0.20 ref. ??12 b 0.18 0.23 0.30 l 0.30 0.40 0.50 d, e 5.00 bsc notes: 1. dimensioning and tolerances c onform to asme y14.5m. - 1994 2. package warpage max 0.05 mm. 3. ?b? applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal tip. 4. the package weight is approximately 66 mg. 5. the mold compound for this package has a flammability rating of ul94-v0 with an oxygen index of 28 minimum/54 typical. 6. the recommended reflow profile for this package is de fined by the jedec-020b small body specification. 32 bottom view 1 1 e2 d2 2 3 top view side view a a1 a2 a3 2 3 pin1 id 0.50 dia. b 32 b e l pin1 id 0.20 r. e e e1 d d1
aero+ 46 rev. 1.3 d ocument c hange l ist revision 1.0 to revision 1.1 this document corresponds to the following: si4200db revision e (dual band lna) or si4200 revision f (triple band lna) si4201 revision c si4134t revision a "3. bill of materials" on page 17 updated l1?-l3 with 0402 sizes. "10. ordering guide" on page 42 updated to include lead-free ordering option. "11. package outline: si4200-g-gm and si4200db- bm" on page 43 (documentation change only, no change to part) updated d2,e2 dimensions. updated device weight. added notes 5 and 6. "12. package outline: si4201-bm" on page 44 (documentation change only, no change to part) updated l dimension. updated device weight. added notes 5 and 6. "13. package outline: si4134t-bm" on page 45 (documentation change only, no change to part) updated l dimension. updated device weight. added notes 5 and 6. revision 1.1 to revision 1.2 this document corresponds to the following: si4200db revision e (dual band lna) or si4200 revision f (triple band lna) si4201 revision c si4134t revision a "13. package outline: si4134t-bm" on page 45 (documentation change only, no change to part) updated l dimension revision 1.2 to revision 1.3 updated "10. ordering guide" on page 42 to include the si4200-g-gm.
aero+ rev. 1.3 47 n otes :
aero+ 48 rev. 1.3 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, texas 78701 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: aeroinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and aero are trademarks of silicon laboratories inc. other products or brand names mentioned herein are tradema rks or registered trademarks of their respective holder the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon labo ratories assumes no responsib ility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further not ice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of t he application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental da mages. silicon laboratories products are not designed, intended, or authorized for use in applica- tions intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such uni ntended or unauthorized application, buye r shall indemnify and hold sili con laboratories harmless against all claims and damages.

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